On Tue, Oct 24, 2023 at 10:41:57PM +0000, Oliver Upton wrote: > On Tue, Oct 24, 2023 at 06:25:33PM +0100, Marc Zyngier wrote: > > On Mon, 23 Oct 2023 19:55:10 +0100, Miguel Luis <miguel.luis@xxxxxxxxxx> wrote: > > > Also, could you please explain what is happening at PSTATE.EL == EL1 > > > and if EL2Enabled() && HCR_EL2.NV == ‘1’ ? > > > > We directly take the trap and not forward it. This isn't exactly the > > letter of the architecture, but at the same time, treating these > > registers as RAZ/WI is the only valid implementation. I don't > > immediately see a problem with taking this shortcut. > > Ugh, that's annoying. The other EL2 views of AArch32 state UNDEF if EL1 > doesn't implement AArch32. It'd be nice to get a relaxation in the > architecture to allow an UNDEF here. Correction (I wasn't thinking): RES0 behavior should be invariant, much like the UNDEF behavior of the other AA32-specific registers. -- Thanks, Oliver
