On Tue, Oct 17, 2023 at 9:58 AM Mingwei Zhang <mizhang@xxxxxxxxxx> wrote: > > On Tue, Oct 17, 2023 at 3:24 AM Manali Shukla <manali.shukla@xxxxxxx> wrote: > > > > On 10/11/2023 7:45 PM, Peter Zijlstra wrote: > > > On Mon, Oct 09, 2023 at 10:33:41PM +0530, Manali Shukla wrote: > > >> Hi all, > > >> > > >> I would like to add following things to the discussion just for the awareness of > > >> everyone. > > >> > > >> Fully virtualized PMC support is coming to an upcoming AMD SoC and we are > > >> working on prototyping it. > > >> > > >> As part of virtualized PMC design, the PERF_CTL registers are defined as Swap > > >> type C: guest PMC states are loaded at VMRUN automatically but host PMC states > > >> are not saved by hardware. > > > > > > Per the previous discussion, doing this while host has active counters > > > that do not have ::exclude_guest=1 is invalid and must result in an > > > error. > > > > > > > Yeah, exclude_guest should be enforced on host, while host has active PMC > > counters and VPMC is enabled. > > > > > Also, I'm assuming it is all optional, a host can still profile a guest > > > if all is configured just so? > > > > > > > Correct, host should be able to profile guest, if VPMC is not enabled. > > > > >> If hypervisor is using the performance counters, it > > >> is hypervisor's responsibility to save PERF_CTL registers to host save area > > >> prior to VMRUN and restore them after VMEXIT. > > > > > > Does VMEXIT clear global_ctrl at least? > > > > > > > global_ctrl will be initialized to reset value(0x3F) during VMEXIT. Similarly, > > all the perf_ctl and perf_ctr are initialized to reset values(0) at VMEXIT. > > Are these guest values (automatically) saved in the guest area of VMCB > on VMEXIT? > Never mind on this one. So, if both values are in Type C, then they should be saved to the guest area of VMCB on VMEXIT (according to APM vol 2 Table B-3). So, this means KVM does not need to intercept these MSRs on pass-through implementation. Thanks. -Mingwei -Mingwei
