On Tue, Oct 17, 2023 at 3:24 AM Manali Shukla <manali.shukla@xxxxxxx> wrote: > > On 10/11/2023 7:45 PM, Peter Zijlstra wrote: > > On Mon, Oct 09, 2023 at 10:33:41PM +0530, Manali Shukla wrote: > >> Hi all, > >> > >> I would like to add following things to the discussion just for the awareness of > >> everyone. > >> > >> Fully virtualized PMC support is coming to an upcoming AMD SoC and we are > >> working on prototyping it. > >> > >> As part of virtualized PMC design, the PERF_CTL registers are defined as Swap > >> type C: guest PMC states are loaded at VMRUN automatically but host PMC states > >> are not saved by hardware. > > > > Per the previous discussion, doing this while host has active counters > > that do not have ::exclude_guest=1 is invalid and must result in an > > error. > > > > Yeah, exclude_guest should be enforced on host, while host has active PMC > counters and VPMC is enabled. > > > Also, I'm assuming it is all optional, a host can still profile a guest > > if all is configured just so? > > > > Correct, host should be able to profile guest, if VPMC is not enabled. > > >> If hypervisor is using the performance counters, it > >> is hypervisor's responsibility to save PERF_CTL registers to host save area > >> prior to VMRUN and restore them after VMEXIT. > > > > Does VMEXIT clear global_ctrl at least? > > > > global_ctrl will be initialized to reset value(0x3F) during VMEXIT. Similarly, > all the perf_ctl and perf_ctr are initialized to reset values(0) at VMEXIT. Are these guest values (automatically) saved in the guest area of VMCB on VMEXIT? > > >> In order to tackle PMC overflow > >> interrupts in guest itself, NMI virtualization or AVIC can be used, so that > >> interrupt on PMC overflow in guest will not leak to host. > > > > Can you please clarify -- AMD has this history with very dodgy PMI > > boundaries. See the whole amd_pmu_adjust_nmi_window() crud. Even the > > PMUv2 update didn't fix that nonsense. > > > > How is any virt stuff supposed to fix this? If the hardware is late > > delivering PMI, what guarantees a guest PMI does not land in host > > context and vice-versa? > > > > How does NMI virtualization (what even is that) or AVIC (I'm assuming > > that's a virtual interrupt controller) help? > > > > When NMI virtualization is enabled and source of VNMI is in guest, micro code will > make sure that VNMI will directly be delivered to the guest (even if NMI was late > delivered), so there is no issue of leaking guest NMI to the host. > > > Please make very sure, with your hardware team, that PMI must not be > > delivered after clearing global_ctrl (preferably) or at the very least, > > there exists a sequence of operations that provides a hard barrier > > to order PMI. > > > We are verifying all the corner cases, while prototyping PMC virtualization. > As of now, we don't see guest NMIs leaking to host issue. But latency issues > still stays. How long is the latency? From the existing code (amd_pmu_disable_all() => amd_pmu_check_overflow()), it seems to take up to 50 microseconds in amd_pmu_check_overflow(). But I wonder how much in reality. Thanks. -Mingwei >
