On 10/5/23 18:41, Jim Mattson wrote:
I hope I'm not throwing stones from a glass house here...
But I'm struggling to think of cases where Intel has read-only
"defeature bits" like this one. There are certainly things like
MSR_IA32_MISC_ENABLE_FAST_STRING that can be toggled, but read-only
indicators of a departure from established architecture seems ...
suboptimal.
It's arguable that TDX changed a bunch of architecture like causing
exceptions on CPUID and MSRs that never caused exceptions before and
_that_ constitutes a defeature. But that's the least of the problems
for a TDX VM. 😄
(Seriously, I'm not trying to shame Intel's x86 fellow travelers here,
just trying to make sure I'm not missing something).
Intel's defeature bits that I know of are:
CPUID.(EAX=7,ECX=0):EBX[bit 13] (Haswell) - "Deprecates FPU CS and FPU
DS values if 1."
CPUID.(EAX=7,ECX=0):EBX[bit 6] (Skylake) - "FDP_EXCPTN_ONLY. x87 FPU
Data Pointer updated only on x87 exceptions if 1."
And for AMD, to get the full landscape:
- CPUID(EAX=8000_0021h).EAX[0], "Processor ignores nested data breakpoints"
- CPUID(EAX=8000_0021h).EAX[9], "SMM_CTL MSR is not present" (the MSR
used to be always present if SVM is available)
AMD had a few processors without X86_BUG_NULL_SEG that do not expose
X86_FEATURE_NULL_SEL_CLR_BASE, but that's conservative so not a big deal.
Paolo
