On Mon, Sep 25, 2023 at 07:08:53PM +0530, Anup Patel wrote:
> Add an entry for the Zicond extension to the riscv,isa-extensions property.
>
> Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx>
> ---
> Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index cad8ef68eca7..3f0b47686080 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -225,6 +225,12 @@ properties:
> ratified in the 20191213 version of the unprivileged ISA
> specification.
>
> + - const: zicond
> + description:
> + The standard Zicond extension for conditional arithmetic and
> + conditional-select/move operations as ratified in commit 95cf1f9
> + ("Add changes requested by Ved during signoff") of riscv-zicond.
> +
> - const: zicsr
> description: |
> The standard Zicsr extension for control and status register
> --
> 2.34.1
>
Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
