On Mon, Sep 25, 2023 at 07:08:51PM +0530, Anup Patel wrote: > Add an entry for the XVentanaCondOps extension to the > riscv,isa-extensions property. > > Signed-off-by: Anup Patel <apatel@xxxxxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 36ff6749fbba..cad8ef68eca7 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -171,6 +171,13 @@ properties: > memory types as ratified in the 20191213 version of the privileged > ISA specification. > > + - const: xventanacondops > + description: | > + The Ventana specific XVentanaCondOps extension for conditional > + arithmetic and conditional-select/move operations defined by the > + Ventana custom extensions specification v1.0.1 (or higher) at > + https://github.com/ventanamicro/ventana-custom-extensions/releases. > + > - const: zba > description: | > The standard Zba bit-manipulation extension for address generation > -- > 2.34.1 > Reviewed-by: Andrew Jones <ajones@xxxxxxxxxxxxxxxx>
