Re: [PATCH v2 09/17] target/riscv: Add Zvbb ISA extension support

[Richard Henderson <richard.henderson@xxxxxxxxxx>]

On 4/17/23 15:58, Lawrence Hunter wrote:
> diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c
> index ac7d28c251e..322dcc0687f 100644
> --- a/accel/tcg/tcg-runtime-gvec.c
> +++ b/accel/tcg/tcg-runtime-gvec.c
> @@ -550,6 +550,17 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc)
>       clear_high(d, oprsz, desc);
>   }
>   
> +void HELPER(gvec_andsc)(void *d, void *a, uint64_t b, uint32_t desc)
> +{
> +    intptr_t oprsz = simd_oprsz(desc);
> +    intptr_t i;
> +
> +    for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
> +        *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & ~b;
> +    }
> +    clear_high(d, oprsz, desc);
> +}
> +
>   void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc)
>   {
>       intptr_t oprsz = simd_oprsz(desc);
> diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h
> index e141a6ab242..d0862004831 100644
> --- a/accel/tcg/tcg-runtime.h
> +++ b/accel/tcg/tcg-runtime.h
> @@ -217,6 +217,7 @@ DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
>   DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
>   
>   DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
> +DEF_HELPER_FLAGS_4(gvec_andsc, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)

The accel/tcg/ patch must be separate.
And I think "andcs" is the proper name.

> +static void tcg_gen_gvec_andsc(unsigned vece, uint32_t dofs, uint32_t aofs,
> +                               TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
> +{
> +    static GVecGen2s g = {
> +        .fni8 = tcg_gen_andc_i64,
> +        .fniv = tcg_gen_andc_vec,
> +        .fno = gen_helper_gvec_andsc,
> +        .prefer_i64 = TCG_TARGET_REG_BITS == 64,
> +    };
> +
> +    g.vece = vece;
> +
> +    tcg_gen_dup_i64(vece, c, c);
> +    tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g);
> +}

This belongs in tcg-op-gvec.c.
The .vece member should be constant as MO_64.
See tcg_gen_gvec_ands from whence you copied this.

> +static void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs,
> +                               TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz)
> +{
> +    TCGv_i32 tmp = tcg_temp_new_i32();
> +    tcg_gen_sub_i32(tmp, tcg_constant_i32(1 << (vece + 3)), shift);
> +    tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz);
> +}

This could plausibly go into tcg-op-gvec.c as well.
To be followed up by proper backend support (which was omitted before because there were 
no users).


r~