This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh, Zvksh,
Zvkg, and Zvksed of the draft RISC-V vector cryptography extensions as per the
v20230407 version of the specification(1) (3206f07). This is an update to the
patchset submitted to qemu-devel on Friday, 10 Mar 2023 16:03:01 +0000.
We've included the following refactorings:
- squashed commits into one commit per extension with separate commits for
each refactoring
- unified trans_rvzvk*.c.inc files into one trans_rvvk.c.inc
- style fixes in insn32.decode and other files
- added macros for EGS values in translation functions.
We've also updated from v20230303 to v20230407 of the spec:
- Zvkb has been split into Zvbb and Zvbc
- vbrev, vclz, vctz, vcpop and vwsll have been added to Zvbb.
Please note that the Zvkt data-independent execution latency extension (and all
extensions including it) has not been implemented, and we would recommend not
using these patches in an environment where timing attacks are an issue.
Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink
sponsored by SiFive, as well as Max Chou and Frank Chang from SiFive.
For convenience we have created a git repo with our patches on top of a recent
master. https://github.com/CodethinkLabs/qemu-ct
1. https://github.com/riscv/riscv-crypto/releases
Dickon Hood (3):
target/riscv: Refactor translation of vector-widening instruction
qemu/bitops.h: Limit rotate amounts
target/riscv: Add Zvbb ISA extension support
Kiran Ostrolenk (5):
target/riscv: Refactor some of the generic vector functionality
target/riscv: Refactor vector-vector translation macro
target/riscv: Refactor some of the generic vector functionality
qemu/host-utils.h: Add clz and ctz functions for lower-bit integers
target/riscv: Add Zvknh ISA extension support
Lawrence Hunter (2):
target/riscv: Add Zvbc ISA extension support
target/riscv: Add Zvksh ISA extension support
Max Chou (3):
crypto: Create sm4_subword
crypto: Add SM4 constant parameter CK
target/riscv: Add Zvksed ISA extension support
Nazar Kazakov (4):
target/riscv: Move vector translation checks
target/riscv: Add Zvkned ISA extension support
target/riscv: Add Zvkg ISA extension support
target/riscv: Expose Zvk* and Zvb[b,c] cpu properties
accel/tcg/tcg-runtime-gvec.c | 11 +
accel/tcg/tcg-runtime.h | 1 +
crypto/sm4.c | 10 +
include/crypto/sm4.h | 9 +
include/qemu/bitops.h | 24 +-
include/qemu/host-utils.h | 54 ++
target/arm/tcg/crypto_helper.c | 10 +-
target/riscv/cpu.c | 39 +
target/riscv/cpu.h | 8 +
target/riscv/helper.h | 95 ++
target/riscv/insn32.decode | 58 ++
target/riscv/insn_trans/trans_rvv.c.inc | 145 ++-
target/riscv/insn_trans/trans_rvvk.c.inc | 617 +++++++++++++
target/riscv/meson.build | 4 +-
target/riscv/op_helper.c | 6 +
target/riscv/translate.c | 1 +
target/riscv/vcrypto_helper.c | 1052 ++++++++++++++++++++++
target/riscv/vector_helper.c | 243 +----
target/riscv/vector_internals.c | 81 ++
target/riscv/vector_internals.h | 228 +++++
20 files changed, 2362 insertions(+), 334 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvvk.c.inc
create mode 100644 target/riscv/vcrypto_helper.c
create mode 100644 target/riscv/vector_internals.c
create mode 100644 target/riscv/vector_internals.h
--
2.40.0
