Re: [PATCH v2 02/17] target/riscv: Refactor vector-vector translation macro

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On 4/17/23 15:58, Lawrence Hunter wrote:
From: Kiran Ostrolenk <kiran.ostrolenk@xxxxxxxxxxxxxxx>

Factor the non SEW-specific stuff out of `GEN_OPIVV_TRANS` into
function `opivv_trans` (similar to `opivi_trans`). `opivv_trans` will be
used in proceeding vector-crypto commits.

Signed-off-by: Kiran Ostrolenk <kiran.ostrolenk@xxxxxxxxxxxxxxx>
---
  target/riscv/insn_trans/trans_rvv.c.inc | 62 +++++++++++++------------
  1 file changed, 32 insertions(+), 30 deletions(-)

Nice code movement, so

Reviewed-by: Richard Henderson <richard.henderson@xxxxxxxxxx>



diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index f2e3d385152..4106bd69949 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1643,38 +1643,40 @@ GEN_OPIWX_WIDEN_TRANS(vwadd_wx)
  GEN_OPIWX_WIDEN_TRANS(vwsubu_wx)
  GEN_OPIWX_WIDEN_TRANS(vwsub_wx)
+static bool opivv_trans(uint32_t vd, uint32_t vs1, uint32_t vs2, uint32_t vm,
+                        gen_helper_gvec_4_ptr *fn, DisasContext *s)
+{
+    uint32_t data = 0;
+    TCGLabel *over = gen_new_label();
+    tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
+    tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);

Existing nit: the first brcondi is redundant with the second, since (unsigned)x >= 0 is always true.


r~



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