On Sat, Apr 08, 2023 at 05:04:23PM +0100, Marc Zyngier wrote: > When taking an exception between the EL1&0 translation regime and > the EL2 translation regime, the page table walker is allowed to > complete the walks started from EL0 or EL1 while running at EL2. > > It means that altering the system registers that define the EL1&0 > translation regime is fraught with danger *unless* we wait for > the completion of such walk with a DSB (R_LFHQG and subsequent > statements in the ARM ARM). We already did the right thing for > other external agents (SPE, TRBE), but not the PTW. > > Rework the existing SPE/TRBE synchronisation to include the PTW, > and add the missing DSB on guest exit. > > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> Reviewed-by: Oliver Upton <oliver.upton@xxxxxxxxx> -- Thanks, Oliver
