It recently became apparent that the way we switch our EL1&0
translation regime is not entirely fool proof.
On taking an exception from EL1&0 to EL2(&0), the page table walker is
allowed to carry on with speculative walks started from EL1&0 while
running at EL2 (see R_LFHQG). Given that the PTW may be actively using
the EL1&0 system registers, the only safe way to deal with it is to
issue a DSB before changing any of it.
We already did the right thing for SPE and TRBE, but ignored the PTW
for unknown reasons (probably because the architecture wasn't crystal
clear at the time).
This requires a bit of surgery in the nvhe code, though most of these
patches are comments so that my future self can understand the purpose
of these barriers. The VHE code is largely unaffected, thanks to the
DSB in the context switch.
The last patch isn't directly related, but a superfluous ISB was
spotted while working on this series.
- From v1 [1]
- Upgraded TLBIs' dsb(ishst) to dsb(ish) to cover the PTW's required
barrier (thanks to Oliver for spotting the issue)
- Split the nVHE patch into 3 distinct patches for ease of
reviewing.
- Brought the extra ISB patch into this series despite having been
previously posted separately.
[1] https://lore.kernel.org/r/ZC75v6kEe06omSc6@xxxxxxxxx
Marc Zyngier (5):
KVM: arm64: nvhe: Synchronise with page table walker on vcpu run
KVM: arm64: nvhe: Synchronise with page table walker on TLBI
KVM: arm64: pkvm: Document the side effects of
kvm_flush_dcache_to_poc()
KVM: arm64: vhe: Synchronise with page table walker on MMU update
KVM: arm64: vhe: Drop extra isb() on guest exit
arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 --
arch/arm64/kvm/hyp/nvhe/mem_protect.c | 7 +++++++
arch/arm64/kvm/hyp/nvhe/switch.c | 18 ++++++++++++++++++
arch/arm64/kvm/hyp/nvhe/tlb.c | 24 +++++++++++++++++++-----
arch/arm64/kvm/hyp/vhe/switch.c | 7 +++----
arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 12 ++++++++++++
6 files changed, 59 insertions(+), 11 deletions(-)
--
2.34.1
