Starting with Zen4, core PMU on AMD platforms such as Genoa and Ryzen-7000 will support PerfMonV2, and it is also compatible with legacy PERFCTR_CORE behavior and MSR addresses. If you don't have access to the hardware specification, the commits d6d0c7f681fd..7685665c390d for host perf can also bring a quick overview. Its main change is the addition of three MSR's equivalent to Intel V2, namely global_ctrl, global_status, global_status_clear. It is worth noting that this feature is very attractive for reducing the overhead of PMU virtualization, since multiple MSR accesses to multiple counters will be replaced by a single access to the global register, plus more accuracy gain when multiple guest counters are used. All related testcases are passed on a Genoa box. Please feel free to run more tests, add more or share comments. Patch 0001-0007 could be applied earlier, which may help reduce the burden on industrious reviewers. Previous: https://lore.kernel.org/kvm/20230214050757.9623-1-likexu@xxxxxxxxxxx/ V4 -> V5 Changelog: - Avoid pronouns in the changelogs and comments; (Sean) - Drop the assumption that KVM can blindly set v2 without changes; (Sean) - Grab host CPUID and clear here (instead of setting); (Sean) - Clarification of behaviours from spec-defined and HW observations; (Sean) - Drop the use of the intermediate "entry"; (Sean) - Use BUILD_BUG_ON() to avoid potential null-pointer deref bug; (Sean) - Add a patch to cap nr_arch_gp_counters in the common flow; (Sean) - Add sanitize check for pmu->nr_arch_gp_counters; (Sean) - Rewrite changelogs which doesn't depend on the shortlog; (Sean) - State what the patch actually does, not "should do"; (Sean) - Drop the useless multiple line comment; (Sean) - Apply a better short log; (Sean) - Drop the performance blurb; (Sean) - Drop the "The", i.e. just "AMD PerfMonV2 defines ..."; (Sean) - s/hanlders/handlers; (Sean) - s/intel/Intel; (Sean) - Drop useless message on pmc_is_globally_enabled(); (Sean) - Tweak "return 1" to follow the patterns for other MSR helpers; (Sean) - Add assumptions about reusing global_ovf_ctrl_mask; (Sean) Like Xu (10): KVM: x86/pmu: Expose reprogram_counters() in pmu.h KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met KVM: x86/pmu: Forget PERFCTR_CORE if the min num of counters isn't met KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag KVM: x86/svm/pmu: Add AMD PerfMonV2 support KVM: x86/cpuid: Add AMD CPUID ExtPerfMonAndDbg leaf 0x80000022 arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - arch/x86/kvm/cpuid.c | 30 +++++++++- arch/x86/kvm/pmu.c | 83 +++++++++++++++++++++++--- arch/x86/kvm/pmu.h | 32 +++++++++- arch/x86/kvm/reverse_cpuid.h | 7 +++ arch/x86/kvm/svm/pmu.c | 67 +++++++++++++++------ arch/x86/kvm/svm/svm.c | 19 +++++- arch/x86/kvm/vmx/pmu_intel.c | 32 ++-------- arch/x86/kvm/x86.c | 10 ++++ 9 files changed, 221 insertions(+), 60 deletions(-) base-commit: dfdeda67ea2dac57d2d7506d65cfe5a0878ad285 -- 2.40.0
