On Fri, Apr 07, 2023, Like Xu wrote: > On 7/4/2023 7:45 am, Sean Christopherson wrote: > > On Tue, Feb 14, 2023, Like Xu wrote: > > > From: Like Xu <likexu@xxxxxxxxxxx> > > > > > > If the user space sets reserved bits when restoring the MSR_CORE_ > > > PERF_GLOBAL_STATUS register, these bits will be accidentally returned > > > when the guest runs a read access to this register, and cannot be cleared > > > up inside the guest, which makes the guest's PMI handler very confused. > > > > The changelog needs to state what the patch actually does. > > > > > Signed-off-by: Like Xu <likexu@xxxxxxxxxxx> > > > --- > > > arch/x86/kvm/vmx/pmu_intel.c | 2 +- > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c > > > index 904f832fc55d..aaea25d2cae8 100644 > > > --- a/arch/x86/kvm/vmx/pmu_intel.c > > > +++ b/arch/x86/kvm/vmx/pmu_intel.c > > > @@ -397,7 +397,7 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) > > > reprogram_fixed_counters(pmu, data); > > > break; > > > case MSR_CORE_PERF_GLOBAL_STATUS: > > > - if (!msr_info->host_initiated) > > > + if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) > > > > This is wrong. Bits 60:58 are reserved in IA32_PERF_GLOBAL_OVF_CTRL, but are > > ASCI, CTR_FREEZE, and LBR_FREEZE respectively in MSR_CORE_PERF_GLOBAL_STATUS. > > CTR_FREEZE and LBR_FREEZE are only required for the guest CPUID.0AH: EAX[7:0]>3. > PMU support (ASCI bit) for guest SGX isn't supported either. > > So for now, reusing pmu->global_ovf_ctrl_mask here is effective enough. And "good enough for now" is exactly how we end up with bugs, especially when "good enough" relies on assumptions that aren't well documented.
