On Sun, 02 Apr 2023 19:37:29 +0100, Jing Zhang <jingzhangos@xxxxxxxxxx> wrote: > > This patchset refactors/adds code to support writable per guest CPU ID feature > registers. Part of the code/ideas are from > https://lore.kernel.org/all/20220419065544.3616948-1-reijiw@xxxxxxxxxx . > No functional change is intended in this patchset. With the new CPU ID feature > registers infrastructure, only writtings of ID_AA64PFR0_EL1.[CSV2|CSV3], > ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon are allowed as KVM does before. > > Writable (Configurable) per guest CPU ID feature registers are useful for > creating/migrating guest on ARM CPUs with different kinds of features. > > --- > > * v4 -> v5 > - Rebased to 2fad20ae05cb (kvmarm/next) > Merge branch kvm-arm64/selftest/misc-6,4 into kvmarm-master/next Please don't do that. Always use a stable, tagged commit, not some random "commit of the day". If there is a dependency, indicate the *exact* dependency. Yes, x86 is managed differently. I'm never going to apply anything on top of an arbitrary commit, so this makes it difficult for both you and I. I understand that you want to avoid conflicts, but I really don't mind resolving those. So please stick to existing tags as a base, and describe the dependencies you have (in this case, the locking series). Thanks, M. -- Without deviation from the norm, progress is not possible.
