This patchset refactors/adds code to support writable per guest CPU ID feature registers. Part of the code/ideas are from https://lore.kernel.org/all/20220419065544.3616948-1-reijiw@xxxxxxxxxx . No functional change is intended in this patchset. With the new CPU ID feature registers infrastructure, only writtings of ID_AA64PFR0_EL1.[CSV2|CSV3], ID_AA64DFR0_EL1.PMUVer and ID_DFR0_ELF.PerfMon are allowed as KVM does before. Writable (Configurable) per guest CPU ID feature registers are useful for creating/migrating guest on ARM CPUs with different kinds of features. --- * v4 -> v5 - Rebased to 2fad20ae05cb (kvmarm/next) Merge branch kvm-arm64/selftest/misc-6,4 into kvmarm-master/next - Use kvm->arch.config_lock to guard update to multiple VM scope idregs to avoid lock inversion - Add back IDREG() macro for idregs access - Refactor struct id_reg_desc by using existing infrastructure. - Addressed many other comments from Marc. * v3 -> v4 - Remove IDREG() macro for ID reg access, use simple array access instead - Rename kvm_arm_read_id_reg_with_encoding() to kvm_arm_read_id_reg() - Save perfmon value in ID_DFR0_EL1 instead of pmuver - Update perfmon in ID_DFR0_EL1 and pmuver in ID_AA64DFR0_EL1 atomically - Remove kvm_vcpu_has_pmu() in macro kvm_pmu_is_3p5() - Improve ID register sanity checking in kvm_arm_check_idreg_table() * v2 -> v3 - Rebased to 96a4627dbbd4 (kvmarm/next) Merge tag ' https://github.com/oupton/linux tags/kvmarm-6.3' from into kvmarm-master/next - Add id registere emulation entry point function emulate_id_reg - Fix consistency for ID_AA64DFR0_EL1.PMUVer and ID_DFR0_EL1.PerfMon - Improve the checking for id register table by ensuring that every entry has the correct id register encoding. - Addressed other comments from Reiji and Marc. * v1 -> v2 - Rebase to 7121a2e1d107 (kvmarm/next) Merge branch kvm-arm64/nv-prefix into kvmarm/next - Address writing issue for PMUVer [1] https://lore.kernel.org/all/20230201025048.205820-1-jingzhangos@xxxxxxxxxx [2] https://lore.kernel.org/all/20230212215830.2975485-1-jingzhangos@xxxxxxxxxx [3] https://lore.kernel.org/all/20230228062246.1222387-1-jingzhangos@xxxxxxxxxx [4] https://lore.kernel.org/all/20230317050637.766317-1-jingzhangos@xxxxxxxxxx --- Jing Zhang (6): KVM: arm64: Move CPU ID feature registers emulation into a separate file KVM: arm64: Save ID registers' sanitized value per guest KVM: arm64: Use per guest ID register for ID_AA64PFR0_EL1.[CSV2|CSV3] KVM: arm64: Use per guest ID register for ID_AA64DFR0_EL1.PMUVer KVM: arm64: Introduce ID register specific descriptor KVM: arm64: Refactor writings for PMUVer/CSV2/CSV3 arch/arm64/include/asm/cpufeature.h | 5 + arch/arm64/include/asm/kvm_host.h | 34 +- arch/arm64/kernel/cpufeature.c | 8 +- arch/arm64/kvm/Makefile | 2 +- arch/arm64/kvm/arm.c | 24 +- arch/arm64/kvm/hyp/nvhe/sys_regs.c | 7 - arch/arm64/kvm/id_regs.c | 790 ++++++++++++++++++++++++++++ arch/arm64/kvm/sys_regs.c | 466 ++-------------- arch/arm64/kvm/sys_regs.h | 29 + include/kvm/arm_pmu.h | 5 +- 10 files changed, 897 insertions(+), 473 deletions(-) create mode 100644 arch/arm64/kvm/id_regs.c base-commit: 2fad20ae05cbcbd1a34272ddd8e27975b4ddcabf -- 2.40.0.348.gf938b09366-goog
