On 3/28/23 11:16, Like Xu wrote:
If IA32_PERF_CAPABILITIES.FW_WRITE[bit 13] =1, each IA32_PMCi is
accompanied by a
corresponding alias address starting at 4C1H for IA32_A_PMC0.
The bit width of the performance monitoring counters is specified in
CPUID.0AH:EAX[23:16].
If IA32_A_PMCi is present, the 64-bit input value (EDX:EAX) of WRMSR to
IA32_A_PMCi will cause
IA32_PMCi to be updated by:
COUNTERWIDTH =
CPUID.0AH:EAX[23:16] bit width of the performance monitoring
counter
IA32_PMCi[COUNTERWIDTH-1:32] := EDX[COUNTERWIDTH-33:0]);
IA32_PMCi[31:0] := EAX[31:0];
EDX[63:COUNTERWIDTH] are reserved
---
Some might argue that this is all talking about GP counters, not
fixed counters. In fact, the full-width write hw behaviour is
presumed to do the same thing for all counters.
But the above behavior, and the #GP, is only true for IA32_A_PMCi (the
full-witdh MSR). Did I understand correctly that the behavior for fixed
counters is changed without introducing an alias MSR?
Paolo
