On Thu, 11 Mar 2010, Nick Piggin wrote: > On Thu, Mar 11, 2010 at 03:10:47AM +0000, Jamie Lokier wrote: > > Paul Brook wrote: > > > > > In a cross environment that becomes extremely hairy. For example the x86 > > > > > architecture effectively has an implicit write barrier before every > > > > > store, and an implicit read barrier before every load. > > > > > > > > Btw, x86 doesn't have any implicit barriers due to ordinary loads. > > > > Only stores and atomics have implicit barriers, afaik. > > > > > > As of March 2009[1] Intel guarantees that memory reads occur in > > > order (they may only be reordered relative to writes). It appears > > > AMD do not provide this guarantee, which could be an interesting > > > problem for heterogeneous migration.. > > > > (Summary: At least on AMD64, it does too, for normal accesses to > > naturally aligned addresses in write-back cacheable memory.) > > > > Oh, that's interesting. Way back when I guess we knew writes were in > > order and it wasn't explicit that reads were, hence smp_rmb() using a > > locked atomic. > > > > Here is a post by Nick Piggin from 2007 with links to Intel _and_ AMD > > documents asserting that reads to cacheable memory are in program order: > > > > http://lkml.org/lkml/2007/9/28/212 > > Subject: [patch] x86: improved memory barrier implementation > > > > Links to documents: > > > > http://developer.intel.com/products/processor/manuals/318147.pdf > > http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24593.pdf > > > > The Intel link doesn't work any more, but the AMD one does. > > It might have been merged into their development manual now. It was (http://www.intel.com/products/processor/manuals/): Intel╝ 64 Architecture Memory Ordering White Paper This document has been merged into Volume 3A of Intel 64 and IA-32 Architectures Software Developer's Manual. [..snip..] -- mailto:av1474@xxxxxxxx
