> > In a cross environment that becomes extremely hairy. For example the x86 > > architecture effectively has an implicit write barrier before every > > store, and an implicit read barrier before every load. > > Btw, x86 doesn't have any implicit barriers due to ordinary loads. > Only stores and atomics have implicit barriers, afaik. As of March 2009[1] Intel guarantees that memory reads occur in order (they may only be reordered relative to writes). It appears AMD do not provide this guarantee, which could be an interesting problem for heterogeneous migration.. Paul [*] The most recent docs I have handy. Up to and including Core-2 Duo. -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
