On 03/10/2010 06:38 AM, Cam Macdonell wrote:
On Tue, Mar 9, 2010 at 5:03 PM, Paul Brook<paul@xxxxxxxxxxxxxxxx> wrote:
In a cross environment that becomes extremely hairy. For example the x86
architecture effectively has an implicit write barrier before every
store, and an implicit read barrier before every load.
Btw, x86 doesn't have any implicit barriers due to ordinary loads.
Only stores and atomics have implicit barriers, afaik.
As of March 2009[1] Intel guarantees that memory reads occur in order (they
may only be reordered relative to writes). It appears AMD do not provide this
guarantee, which could be an interesting problem for heterogeneous migration..
Paul
[*] The most recent docs I have handy. Up to and including Core-2 Duo.
Interesting, but what ordering would cause problems that AMD would do
but Intel wouldn't? Wouldn't that ordering cause the same problems
for POSIX shared memory in general (regardless of Qemu) on AMD?
If some code was written for the Intel guarantees it would break if
migrated to AMD. Of course, it would also break if run on AMD in the
first place.
I think shared memory breaks migration anyway.
Until someone implements distributed shared memory.
--
error compiling committee.c: too many arguments to function
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