On 2023/2/21 18:18, maobibo wrote:
在 2023/2/21 16:14, Paolo Bonzini 写道:
On 2/21/23 07:59, maobibo wrote:
Also, why does the world switch code need a copy?
There will be problem in world switch code if there is page fault reenter,
since pgd register is shared between root kernel and kvm hypervisor.
World switch entry need be unmapped area, cannot be tlb mapped area.
So if I understand correctly the processor is in direct address translation mode until the "csrwr t0, LOONGARCH_CSR_CRMD" instruction. Where does it leave paged mode?
The processor still in paged mode during world switch context. For example
when vm exits from guest mode to root mode, it executes world switch code
from kvm_vector_entry, PC register points to HVA address, however vmid from
LOONGARCH_CSR_GTLBC is not clear to root mode. If there is page fault
exception, hardware treats it exception from GPA-->HPA rather than that
from HVA --> HPA, since vmid info in CSR_GTLBC is not zero.
In page mode, there are two kinds of address: unmapped address and
tlb mapped address. For unmapped address there is only cachable/uncachable
attribution, but not RWX attr; and there is no tlb handling for it.
For simplicity, unmapped address can be treated as window filtered address.
It will be fully root mode only after this piece of code is executed
during world switch context; vmid is zero and PC points to HVA.
ori t0, zero, CSR_GSTAT_PVM
csrxchg zero, t0, LOONGARCH_CSR_GSTAT
/* Clear GTLBC.TGID field */
csrrd t0, LOONGARCH_CSR_GTLBC
bstrins.w t0, zero, CSR_GTLBC_TGID_SHIFT_END, CSR_GTLBC_TGID_SHIFT
csrwr t0, LOONGARCH_CSR_GTLBC
AFAIK all of these is probably coming from Volume 3 of LoongArch ISA
Manual, which is unfortunately not publicly available at the moment. For
sake of meaningful reviews, when can we expect to get our hands on the
manuals?
--
WANG "xen0n" Xuerui
Linux/LoongArch mailing list: https://lore.kernel.org/loongarch/
