On 2/21/23 07:59, maobibo wrote:
Also, why does the world switch code need a copy?
There will be problem in world switch code if there is page fault reenter,
since pgd register is shared between root kernel and kvm hypervisor.
World switch entry need be unmapped area, cannot be tlb mapped area.
So if I understand correctly the processor is in direct address
translation mode until the "csrwr t0, LOONGARCH_CSR_CRMD" instruction.
Where does it leave paged mode?
Can you please also add comments to kvm_vector_entry explaining the
processor state after a VZ exception entry (interrupts, paging, ...)?
Paolo
