The EXECUTE instruction executes the instruction at the given target address. This address must be halfword aligned, otherwise a specification exception occurs. Add a test for this. Signed-off-by: Nina Schoetterl-Glausch <nsg@xxxxxxxxxxxxx> --- s390x/spec_ex.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/s390x/spec_ex.c b/s390x/spec_ex.c index b6764677..0cd3174f 100644 --- a/s390x/spec_ex.c +++ b/s390x/spec_ex.c @@ -200,6 +200,30 @@ static int short_psw_bit_12_is_0(void) return 0; } +static int odd_ex_target(void) +{ + uint64_t target_addr_pre; + int to = 0, from = 0x0dd; + + asm volatile ( ".pushsection .rodata\n" + "odd_ex_target_pre_insn:\n" + " .balign 2\n" + " . = . + 1\n" + " lr %[to],%[from]\n" + " .popsection\n" + + " larl %[target_addr_pre],odd_ex_target_pre_insn\n" + " ex 0,1(%[target_addr_pre])\n" + : [target_addr_pre] "=&a" (target_addr_pre), + [to] "+d" (to) + : [from] "d" (from) + ); + + assert((target_addr_pre + 1) & 1); + report(to != from, "did not perform ex with odd target"); + return 0; +} + static int bad_alignment(void) { uint32_t words[5] __attribute__((aligned(16))); @@ -241,6 +265,7 @@ static const struct spec_ex_trigger spec_ex_triggers[] = { { "psw_bit_12_is_1", &psw_bit_12_is_1, false, &fixup_invalid_psw }, { "short_psw_bit_12_is_0", &short_psw_bit_12_is_0, false, &fixup_invalid_psw }, { "psw_odd_address", &psw_odd_address, false, &fixup_invalid_psw }, + { "odd_ex_target", &odd_ex_target, true, NULL }, { "bad_alignment", &bad_alignment, true, NULL }, { "not_even", ¬_even, true, NULL }, { NULL, NULL, false, NULL }, -- 2.36.1