On 1/9/23 22:17, Ricardo Koller wrote:
> The arm/pmu test prints the value of counters as %ld. Most tests start
> with counters around 0 or UINT_MAX, so having something like -16 instead of
> 0xffff_fff0 is not very useful.
>
> Report counter values as hexadecimals.
>
> Reported-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
> Signed-off-by: Ricardo Koller <ricarkol@xxxxxxxxxx>
Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx>
Thanks
Eric
> ---
> arm/pmu.c | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arm/pmu.c b/arm/pmu.c
> index 72d0f50..77b0a70 100644
> --- a/arm/pmu.c
> +++ b/arm/pmu.c
> @@ -552,8 +552,8 @@ static void test_mem_access(bool overflow_at_64bits)
> write_sysreg_s(0x3, PMCNTENSET_EL0);
> isb();
> mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp);
> - report_info("counter #0 is %ld (MEM_ACCESS)", read_regn_el0(pmevcntr, 0));
> - report_info("counter #1 is %ld (MEM_ACCESS)", read_regn_el0(pmevcntr, 1));
> + report_info("counter #0 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 0));
> + report_info("counter #1 is 0x%lx (MEM_ACCESS)", read_regn_el0(pmevcntr, 1));
> /* We may measure more than 20 mem access depending on the core */
> report((read_regn_el0(pmevcntr, 0) == read_regn_el0(pmevcntr, 1)) &&
> (read_regn_el0(pmevcntr, 0) >= 20) && !read_sysreg(pmovsclr_el0),
> @@ -568,7 +568,7 @@ static void test_mem_access(bool overflow_at_64bits)
> mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E | pmcr_lp);
> report(read_sysreg(pmovsclr_el0) == 0x3,
> "Ran 20 mem accesses with expected overflows on both counters");
> - report_info("cnt#0 = %ld cnt#1=%ld overflow=0x%lx",
> + report_info("cnt#0=0x%lx cnt#1=0x%lx overflow=0x%lx",
> read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1),
> read_sysreg(pmovsclr_el0));
> }
> @@ -599,7 +599,7 @@ static void test_sw_incr(bool overflow_at_64bits)
> write_sysreg(0x1, pmswinc_el0);
>
> isb();
> - report_info("SW_INCR counter #0 has value %ld", read_regn_el0(pmevcntr, 0));
> + report_info("SW_INCR counter #0 has value 0x%lx", read_regn_el0(pmevcntr, 0));
> report(read_regn_el0(pmevcntr, 0) == pre_overflow,
> "PWSYNC does not increment if PMCR.E is unset");
>
> @@ -616,7 +616,7 @@ static void test_sw_incr(bool overflow_at_64bits)
> isb();
> report(read_regn_el0(pmevcntr, 0) == cntr0, "counter #0 after + 100 SW_INCR");
> report(read_regn_el0(pmevcntr, 1) == 100, "counter #1 after + 100 SW_INCR");
> - report_info("counter values after 100 SW_INCR #0=%ld #1=%ld",
> + report_info("counter values after 100 SW_INCR #0=0x%lx #1=0x%lx",
> read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
> report(read_sysreg(pmovsclr_el0) == 0x1,
> "overflow on counter #0 after 100 SW_INCR");
> @@ -692,7 +692,7 @@ static void test_chained_sw_incr(bool unused)
> report((read_sysreg(pmovsclr_el0) == 0x1) &&
> (read_regn_el0(pmevcntr, 1) == 1),
> "overflow and chain counter incremented after 100 SW_INCR/CHAIN");
> - report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
> + report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0),
> read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
>
> /* 64b SW_INCR and overflow on CHAIN counter*/
> @@ -713,7 +713,7 @@ static void test_chained_sw_incr(bool unused)
> (read_regn_el0(pmevcntr, 0) == cntr0) &&
> (read_regn_el0(pmevcntr, 1) == cntr1),
> "expected overflows and values after 100 SW_INCR/CHAIN");
> - report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
> + report_info("overflow=0x%lx, #0=0x%lx #1=0x%lx", read_sysreg(pmovsclr_el0),
> read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
> }
>
> @@ -745,11 +745,11 @@ static void test_chain_promotion(bool unused)
> mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E);
> report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1),
> "odd counter did not increment on overflow if disabled");
> - report_info("MEM_ACCESS counter #0 has value %ld",
> + report_info("MEM_ACCESS counter #0 has value 0x%lx",
> read_regn_el0(pmevcntr, 0));
> - report_info("CHAIN counter #1 has value %ld",
> + report_info("CHAIN counter #1 has value 0x%lx",
> read_regn_el0(pmevcntr, 1));
> - report_info("overflow counter %ld", read_sysreg(pmovsclr_el0));
> + report_info("overflow counter 0x%lx", read_sysreg(pmovsclr_el0));
>
> /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */
> pmu_reset();
