Hi Ricardo,
On 1/9/23 22:17, Ricardo Koller wrote:
> PMUv3p5 uses 64-bit counters irrespective of whether the PMU is configured
> for overflowing at 32 or 64-bits. The consequence is that tests that check
> the counter values after overflowing should not assume that values will be
> wrapped around 32-bits: they overflow into the other half of the 64-bit
> counters on PMUv3p5.
>
> Fix tests by correctly checking overflowing-counters against the expected
> 64-bit value.
>
> Signed-off-by: Ricardo Koller <ricarkol@xxxxxxxxxx>
Reviewed-by: Eric Auger <eric.auger@xxxxxxxxxx>
Thanks
Eric
> ---
> arm/pmu.c | 38 ++++++++++++++++++++++++++++----------
> 1 file changed, 28 insertions(+), 10 deletions(-)
>
> diff --git a/arm/pmu.c b/arm/pmu.c
> index cd47b14..7f0794d 100644
> --- a/arm/pmu.c
> +++ b/arm/pmu.c
> @@ -54,10 +54,10 @@
> #define EXT_COMMON_EVENTS_LOW 0x4000
> #define EXT_COMMON_EVENTS_HIGH 0x403F
>
> -#define ALL_SET 0xFFFFFFFF
> -#define ALL_CLEAR 0x0
> -#define PRE_OVERFLOW 0xFFFFFFF0
> -#define PRE_OVERFLOW2 0xFFFFFFDC
> +#define ALL_SET 0x00000000FFFFFFFFULL
> +#define ALL_CLEAR 0x0000000000000000ULL
> +#define PRE_OVERFLOW 0x00000000FFFFFFF0ULL
> +#define PRE_OVERFLOW2 0x00000000FFFFFFDCULL
>
> #define PMU_PPI 23
>
> @@ -419,6 +419,22 @@ static bool satisfy_prerequisites(uint32_t *events, unsigned int nb_events)
> return true;
> }
>
> +static uint64_t pmevcntr_mask(void)
> +{
> + /*
> + * Bits [63:0] are always incremented for 64-bit counters,
> + * even if the PMU is configured to generate an overflow at
> + * bits [31:0]
> + *
> + * For more details see the AArch64.IncrementEventCounter()
> + * pseudo-code in the ARM ARM DDI 0487I.a, section J1.1.1.
> + */
> + if (pmu.version >= ID_DFR0_PMU_V3_8_5)
> + return ~0;
> +
> + return (uint32_t)~0;
> +}
> +
> static void test_basic_event_count(void)
> {
> uint32_t implemented_counter_mask, non_implemented_counter_mask;
> @@ -538,6 +554,7 @@ static void test_mem_access(void)
> static void test_sw_incr(void)
> {
> uint32_t events[] = {SW_INCR, SW_INCR};
> + uint64_t cntr0 = (PRE_OVERFLOW + 100) & pmevcntr_mask();
> int i;
>
> if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
> @@ -572,9 +589,8 @@ static void test_sw_incr(void)
> write_sysreg(0x3, pmswinc_el0);
>
> isb();
> - report(read_regn_el0(pmevcntr, 0) == 84, "counter #1 after + 100 SW_INCR");
> - report(read_regn_el0(pmevcntr, 1) == 100,
> - "counter #0 after + 100 SW_INCR");
> + report(read_regn_el0(pmevcntr, 0) == cntr0, "counter #0 after + 100 SW_INCR");
> + report(read_regn_el0(pmevcntr, 1) == 100, "counter #1 after + 100 SW_INCR");
> report_info("counter values after 100 SW_INCR #0=%ld #1=%ld",
> read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
> report(read_sysreg(pmovsclr_el0) == 0x1,
> @@ -625,6 +641,8 @@ static void test_chained_counters(void)
> static void test_chained_sw_incr(void)
> {
> uint32_t events[] = {SW_INCR, CHAIN};
> + uint64_t cntr0 = (PRE_OVERFLOW + 100) & pmevcntr_mask();
> + uint64_t cntr1 = (ALL_SET + 1) & pmevcntr_mask();
> int i;
>
> if (!satisfy_prerequisites(events, ARRAY_SIZE(events)))
> @@ -666,9 +684,9 @@ static void test_chained_sw_incr(void)
>
> isb();
> report((read_sysreg(pmovsclr_el0) == 0x3) &&
> - (read_regn_el0(pmevcntr, 1) == 0) &&
> - (read_regn_el0(pmevcntr, 0) == 84),
> - "expected overflows and values after 100 SW_INCR/CHAIN");
> + (read_regn_el0(pmevcntr, 0) == cntr0) &&
> + (read_regn_el0(pmevcntr, 1) == cntr1),
> + "expected overflows and values after 100 SW_INCR/CHAIN");
> report_info("overflow=0x%lx, #0=%ld #1=%ld", read_sysreg(pmovsclr_el0),
> read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1));
> }
