>From: Tian, Kevin <kevin.tian@xxxxxxxxx> >Not a NVMe guy but obviously Intel should join. I have forwarded this >to internal folks to check the actual status. Intel team has been actively participating in the TPAR definition over last month. The key leadership in NVMe WG, Peter and Nick (from Intel), are on top of this TPAR, and help influence the scope of the TPAR to better support IPU/DPUs. IPU/DPU is a new type of device that desperately needs a standard based live migration solution. Soon, you may also see more Intel people to be part of the SW WG for the NVMe live migration standardization effort. >And I also asked them to prepare a document explaining how this >opaque cmd actually works to address your concerns. There is nothing secret. It's the VF states including VF CSR registers, IO QP states, and the AdminQ state. The AdminQ state may also include the pending AER command. As part of the NVMe live migration standardization effort, it's desirable to standardize the structure as much as we can, and then have an extension for any device specific state that may be required to work around specific design HW limitations.
