On Tue, Dec 06, 2022 at 09:05:05AM -0400, Jason Gunthorpe wrote: > In this case Intel has a real PCI SRIOV VF to expose to the guest, > with a full VF RID. RID? > The proper VFIO abstraction is the variant PCI > driver as this series does. We want to use the variant PCI drivers > because they properly encapsulate all the PCI behaviors (MSI, config > space, regions, reset, etc) without requiring re-implementation of this > in mdev drivers. I don't think the code in this series has any chance of actually working. There is a lot of state associated with a NVMe subsystem, controller and namespace, such as the serial number, subsystem NQN, namespace uniqueue identifiers, Get/Set features state, pending AENs, log page content. Just migrating from one device to another without capturing all this has no chance of actually working. > I don't think we know enough about this space at the moment to fix a > specification to one path or the other, so I hope the TPAR will settle > on something that can support both models in SW and people can try > things out. I've not seen anyone from Intel actually contributing to the live migration TPAR, which is almost two month old by now.
