Re: [kvm-unit-tests PATCH v5 26/27] x86/pmu: Update testcases to cover AMD PMU

[Paolo Bonzini <pbonzini@xxxxxxxxxx>]

On 11/2/22 23:51, Sean Christopherson wrote:
> +		pmu.msr_gp_counter_base = MSR_F15H_PERF_CTR0;
> +		pmu.msr_gp_event_select_base = MSR_F15H_PERF_CTL0;
> +		if (!this_cpu_has(X86_FEATURE_PERFCTR_CORE))
> +			pmu.nr_gp_counters = AMD64_NUM_COUNTERS;
> +		else
> +			pmu.nr_gp_counters = AMD64_NUM_COUNTERS_CORE;
> +

If X86_FEATURE_PERFCTR_CORE is not set, pmu.msr_gp_*_base should point 
to MSR_K7_PERFCTR0/MSR_K7_EVNTSEL0:

diff --git a/lib/x86/pmu.c b/lib/x86/pmu.c
index af68f3a..8d5f69f 100644
--- a/lib/x86/pmu.c
+++ b/lib/x86/pmu.c
@@ -47,10 +47,13 @@ void pmu_init(void)
 		pmu.msr_gp_event_select_base = MSR_F15H_PERF_CTL0;
 		if (this_cpu_has(X86_FEATURE_AMD_PMU_V2))
 			pmu.nr_gp_counters = cpuid(0x80000022).b & 0xf;
-		else if (!this_cpu_has(X86_FEATURE_PERFCTR_CORE))
-			pmu.nr_gp_counters = AMD64_NUM_COUNTERS;
-		else
+		else if (this_cpu_has(X86_FEATURE_PERFCTR_CORE))
 			pmu.nr_gp_counters = AMD64_NUM_COUNTERS_CORE;
+		else {
+			pmu.nr_gp_counters = AMD64_NUM_COUNTERS;
+			pmu.msr_gp_counter_base = MSR_K7_PERFCTR0;
+			pmu.msr_gp_event_select_base = MSR_K7_EVNTSEL0;
+		}

 		pmu.gp_counter_width = PMC_DEFAULT_WIDTH;
 		pmu.gp_counter_mask_length = pmu.nr_gp_counters;

Paolo