On 11/2/22 11:16, Paolo Bonzini wrote: > On 11/2/22 19:14, Dave Hansen wrote: >>> kvm_cpu_cap_mask(CPUID_7_1_EAX, >>> - F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) >>> + F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | F(AMX_FP16) >>> ); >>> kvm_cpu_cap_mask(CPUID_D_1_EAX, >> >> KVM folks, is the idea that every feature that is enumerated to a guest >> needs to be in one of these masks? Or is there something special about >> the features in these masks? > > Yes, all features are vetted manually to see whether they require new > MSRs and the like. Therefore, anything that userspace can set in the > guest's CPUID must be in the list. Makes sense. Intel folks, when you add these bits, can you please include information about the "vetting" that you performed? For example, it would be handy to say: AMX_FP16 is just a new instruction that operates on existing AMX tile registers. It needs no additional enabling on top of the existing kernel AMX enabling.
