On Fri, Oct 21, 2022, Xiaoyao Li wrote: > On 10/21/2022 12:32 AM, Sean Christopherson wrote: > > If we really want to clean up this code, I think the correct approach would be to > > inject #GP on all relevant MSRs if CPUID.MCA==0, e.g. > > It's what I thought of as well. But I didn't find any statement in SDM of > "Accessing Machine Check MSRs gets #GP if no CPUID.MCA" Ugh, stupid SDM. Really old SDMs, e.g. circa 1997, explicity state in the CPUID.MCA entry that: Processor supports the MCG_CAP MSR. But, when Intel introduced the "Architectural MSRs" section (2001 or so), the wording was changed to be less explicit: The Machine Check Architecture, which provides a compatible mechanism for error reporting in P6 family, Pentium 4, and Intel Xeon processors, and future processors, is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported. and the entry in the MSR index just lists P6 as the dependency: IA32_MCG_CAP (MCG_CAP) Global Machine Check Capability (R/O) 06_01H So I think it's technically true that MCG_CAP is supposed to exist iff CPUID.MCA=1, but we'd probably need an SDM change to really be able to enforce that :-(
