Changes since "[RFC PATCH v6 00/36] KVM: x86: eVMCS rework":
- Drop the most controversial TSC_SCALING enablement for Hyper-V on KVM:
- "KVM: nVMX: Enforce unsupported eVMCS in VMX MSRs for host accesses" patch dropped.
- "KVM: nVMX: Support TSC scaling with enlightened VMCS" patch dropped.
- "KVM: selftests: Enable TSC scaling in evmcs selftest" patch dropped.
Original description:
Enlightened VMCS v1 definition was updates to include fields for the
following features:
- PerfGlobalCtrl
- EnclsExitingBitmap
- TSC scaling
- GuestLbrCtl
- CET
- SSP
While the information is missing in the publicly available TLFS, the
updated definition comes with a new feature bit in CPUID.0x4000000A.EBX
(BIT 0) for PerfGlobalCtrl.
Add support for the new revision to KVM. SSP, CET and GuestLbrCtl
features are not currently supported by KVM. Note: for Hyper-V on KVM,
only PerfGlobalCtrl is added as it has a dedicated CPUID bit. The way
how to enable different layouts of eVMSC in a VMM friendly way is still
under discussion.
While on it, implement Sean's idea to use vmcs_config for setting up
L1 VMX control MSRs instead of re-reading host MSRs.
Jim Mattson (1):
KVM: x86: VMX: Replace some Intel model numbers with mnemonics
Sean Christopherson (9):
KVM: x86: Check for existing Hyper-V vCPU in kvm_hv_vcpu_init()
KVM: x86: Report error when setting CPUID if Hyper-V allocation fails
KVM: nVMX: Treat eVMCS as enabled for guest iff Hyper-V is also
enabled
KVM: nVMX: Use CC() macro to handle eVMCS unsupported controls checks
KVM: nVMX: WARN once and fail VM-Enter if eVMCS sees VMFUNC[63:32] !=
0
KVM: nVMX: Don't propagate vmcs12's PERF_GLOBAL_CTRL settings to
vmcs02
KVM: nVMX: Always emulate PERF_GLOBAL_CTRL VM-Entry/VM-Exit controls
KVM: VMX: Don't toggle VM_ENTRY_IA32E_MODE for 32-bit kernels/KVM
KVM: VMX: Adjust CR3/INVPLG interception for EPT=y at runtime, not
setup
Vitaly Kuznetsov (23):
x86/hyperv: Fix 'struct hv_enlightened_vmcs' definition
x86/hyperv: Update 'struct hv_enlightened_vmcs' definition
KVM: x86: Zero out entire Hyper-V CPUID cache before processing
entries
KVM: nVMX: Refactor unsupported eVMCS controls logic to use 2-d array
KVM: VMX: Define VMCS-to-EVMCS conversion for the new fields
KVM: nVMX: Support several new fields in eVMCSv1
KVM: x86: hyper-v: Cache HYPERV_CPUID_NESTED_FEATURES CPUID leaf
KVM: selftests: Add ENCLS_EXITING_BITMAP{,HIGH} VMCS fields
KVM: selftests: Switch to updated eVMCSv1 definition
KVM: nVMX: Support PERF_GLOBAL_CTRL with enlightened VMCS
KVM: VMX: Get rid of eVMCS specific VMX controls sanitization
KVM: VMX: Check VM_ENTRY_IA32E_MODE in setup_vmcs_config()
KVM: VMX: Check CPU_BASED_{INTR,NMI}_WINDOW_EXITING in
setup_vmcs_config()
KVM: VMX: Tweak the special handling of SECONDARY_EXEC_ENCLS_EXITING
in setup_vmcs_config()
KVM: VMX: Extend VMX controls macro shenanigans
KVM: VMX: Move CPU_BASED_CR8_{LOAD,STORE}_EXITING filtering out of
setup_vmcs_config()
KVM: VMX: Add missing VMEXIT controls to vmcs_config
KVM: VMX: Add missing CPU based VM execution controls to vmcs_config
KVM: VMX: Move LOAD_IA32_PERF_GLOBAL_CTRL errata handling out of
setup_vmcs_config()
KVM: nVMX: Always set required-1 bits of pinbased_ctls to
PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
KVM: nVMX: Use sanitized allowed-1 bits for VMX control MSRs
KVM: VMX: Cache MSR_IA32_VMX_MISC in vmcs_config
KVM: nVMX: Use cached host MSR_IA32_VMX_MISC value for setting up
nested MSR
arch/x86/include/asm/hyperv-tlfs.h | 22 +-
arch/x86/include/asm/kvm_host.h | 2 +
arch/x86/kvm/cpuid.c | 18 +-
arch/x86/kvm/hyperv.c | 70 +++--
arch/x86/kvm/hyperv.h | 6 +-
arch/x86/kvm/vmx/capabilities.h | 14 +-
arch/x86/kvm/vmx/evmcs.c | 192 ++++++++-----
arch/x86/kvm/vmx/evmcs.h | 10 +-
arch/x86/kvm/vmx/nested.c | 94 ++++---
arch/x86/kvm/vmx/nested.h | 2 +-
arch/x86/kvm/vmx/vmx.c | 259 ++++++++----------
arch/x86/kvm/vmx/vmx.h | 172 ++++++++++--
.../selftests/kvm/include/x86_64/evmcs.h | 45 ++-
.../selftests/kvm/include/x86_64/vmx.h | 2 +
14 files changed, 584 insertions(+), 324 deletions(-)
--
2.37.2
