On Thu, Jul 28, 2022 at 08:44:30AM -0500, Michael Roth wrote: > Hi Sean, > > With this patch applied, AMD processors that support 52-bit physical Sorry, threading got messed up. This is in reference to: https://lore.kernel.org/lkml/20220420002747.3287931-1-seanjc@xxxxxxxxxx/#r commit 8b9e74bfbf8c7020498a9ea600bd4c0f1915134d Author: Sean Christopherson <seanjc@xxxxxxxxxx> Date: Wed Apr 20 00:27:47 2022 +0000 KVM: x86/mmu: Use enable_mmio_caching to track if MMIO caching is enabled > address will result in MMIO caching being disabled. This ends up > breaking SEV-ES and SNP, since they rely on the MMIO reserved bit to > generate the appropriate NAE MMIO exit event. > > This failure can also be reproduced on Milan by disabling mmio_caching > via KVM module parameter. > > In the case of AMD, guests use a separate physical address range that > and so there are still reserved bits available to make use of the MMIO > caching. This adjustment happens in svm_adjust_mmio_mask(), but since > mmio_caching_enabled flag is 0, any attempts to update masks get > ignored by kvm_mmu_set_mmio_spte_mask(). > > Would adding 'force' parameter to kvm_mmu_set_mmio_spte_mask() that > svm_adjust_mmio_mask() can set to ignore enable_mmio_caching be > reasonable fix, or should we take a different approach? > > Thanks! > > -Mike
