Hi Sean, With this patch applied, AMD processors that support 52-bit physical address will result in MMIO caching being disabled. This ends up breaking SEV-ES and SNP, since they rely on the MMIO reserved bit to generate the appropriate NAE MMIO exit event. This failure can also be reproduced on Milan by disabling mmio_caching via KVM module parameter. In the case of AMD, guests use a separate physical address range that and so there are still reserved bits available to make use of the MMIO caching. This adjustment happens in svm_adjust_mmio_mask(), but since mmio_caching_enabled flag is 0, any attempts to update masks get ignored by kvm_mmu_set_mmio_spte_mask(). Would adding 'force' parameter to kvm_mmu_set_mmio_spte_mask() that svm_adjust_mmio_mask() can set to ignore enable_mmio_caching be reasonable fix, or should we take a different approach? Thanks! -Mike
