On Tue, Jul 5, 2022 at 6:38 AM Maxim Levitsky <mlevitsk@xxxxxxxxxx> wrote: > Most of the SMI save state area is reserved, and the handler has no way of knowing > what CPU stored there, it can only access the fields that are reserved in the spec. > > Yes, if the SMI handler really insists it can see that the saved RIP points to an > instruction that follows the STI, but does that really matter? It is allowed by the > spec explicitly anyway. I was just pointing out that the difference between blocking SMI and not blocking SMI is, in fact, observable. > Plus our SMI layout (at least for 32 bit) doesn't confirm to the X86 spec anyway, > we as I found out flat out write over the fields that have other meaning in the X86 spec. Shouldn't we fix that? > Also I proposed to preserve the int shadow in internal kvm state and migrate > it in upper 4 bits of the 'shadow' field of struct kvm_vcpu_events. > Both Paolo and Sean proposed to store the int shadow in the SMRAM instead, > and you didn't object to this, and now after I refactored and implemented > the whole thing you suddently do. I did not see the prior conversations. I rarely get an opportunity to read the list. > However AMD just recently posted a VNMI patch series to avoid > single stepping the CPU when NMI is blocked due to the same reason, because > it is fragile. The vNMI feature isn't available in any shipping processor yet, is it? > Do you really want KVM to single step the guest in this case, to deliver the #SMI? > I can do it, but it is bound to cause lot of trouble. Perhaps you could document this as a KVM erratum...one of many involving virtual SMI delivery.
