On Tue, Jun 21, 2022 at 8:09 AM Maxim Levitsky <mlevitsk@xxxxxxxxxx> wrote: > > When #SMI is asserted, the CPU can be in interrupt shadow > due to sti or mov ss. > > It is not mandatory in Intel/AMD prm to have the #SMI > blocked during the shadow, and on top of > that, since neither SVM nor VMX has true support for SMI > window, waiting for one instruction would mean single stepping > the guest. > > Instead, allow #SMI in this case, but both reset the interrupt > window and stash its value in SMRAM to restore it on exit > from SMM. > > This fixes rare failures seen mostly on windows guests on VMX, > when #SMI falls on the sti instruction which mainfest in > VM entry failure due to EFLAGS.IF not being set, but STI interrupt > window still being set in the VMCS. I think you're just making stuff up! See Note #5 at https://sandpile.org/x86/inter.htm. Can you reference the vendors' documentation that supports this change?
