On Thu, 2022-06-16 at 12:25 +0200, Peter Zijlstra wrote:
> On Thu, Jun 16, 2022 at 04:46:27AM -0400, Yang Weijiang wrote:
>
> > static __always_inline void setup_cet(struct cpuinfo_x86 *c)
> > {
> > + bool kernel_ibt = HAS_KERNEL_IBT &&
> > cpu_feature_enabled(X86_FEATURE_IBT);
> > u64 msr = CET_ENDBR_EN;
> >
> > + if (kernel_ibt)
> > + wrmsrl(MSR_IA32_S_CET, msr);
> >
> > + if (kernel_ibt || cpu_feature_enabled(X86_FEATURE_SHSTK))
> > + cr4_set_bits(X86_CR4_CET);
>
> Does flipping the CR4 and S_CET MSR write not result in simpler code?
I thought it was more defensive to reset S_CET before turning it on
with CR4. Of course CR4.CET could have been left on as well, but if CET
features were actually fully turned on, then we probably wouldn't have
gotten here. Seem reasonable?
>
> >
> > + if (kernel_ibt && !ibt_selftest()) {
> > pr_err("IBT selftest: Failed!\n");
> > setup_clear_cpu_cap(X86_FEATURE_IBT);
>
> Looking at this error path; I think I forgot to clear S_CET here.
>
Yea. I can fix it in the next version of this if you want.
> > return;
> > }
> > }
