Avoid expensive rdmsr on every VM Exit for MSR_IA32_SPEC_CTRL on
eIBRS enabled systems iff the guest only sets IA32_SPEC_CTRL[0] (IBRS)
and not [1] (STIBP) or [2] (SSBD) by not disabling interception in
the MSR bitmap. Note: this logic is only for eIBRS, as Intel's guidance
has long been that eIBRS only needs to be set once, so most guests with
eIBRS awareness should behave nicely. We would not want to accidentally
regress misbehaving guests on pre-eIBRS systems, who might be spamming
IBRS MSR without the hypervisor being able to see it today.
eIBRS enabled guests using just IBRS will only write SPEC_CTRL MSR
once or twice per vCPU on boot, so it is far better to take those
VM exits on boot than having to read and save this msr on every
single VM exit forever. This outcome was suggested on Andrea's commit
2f46993d83ff ("x86: change default to spec_store_bypass_disable=prctl spectre_v2_user=prctl")
however, since interception is still unilaterally disabled, the rdmsr
tax is still there even after that commit.
This is a significant win for eIBRS enabled systems as this rdmsr
accounts for roughly ~50% of time for vmx_vcpu_run() as observed
by perf top disassembly, and is in the critical path for all
VM-Exits, including fastpath exits.
Update relevant comments in vmx_vcpu_run() and opportunistically
update comments for both MSR_IA32_SPEC_CTRL and MSR_IA32_PRED_CMD to
make it clear how L1 vs L2 handling works.
Fixes: 2f46993d83ff ("x86: change default to spec_store_bypass_disable=prctl spectre_v2_user=prctl")
Signed-off-by: Jon Kohler <jon@xxxxxxxxxxx>
Cc: Sean Christopherson <seanjc@xxxxxxxxxx>
Cc: Andrea Arcangeli <aarcange@xxxxxxxxxx>
Cc: Kees Cook <keescook@xxxxxxxxxxxx>
Cc: Josh Poimboeuf <jpoimboe@xxxxxxxxxx>
Cc: Waiman Long <longman@xxxxxxxxxx>
---
v1
- https://lore.kernel.org/all/20220512174427.3608-1-jon@xxxxxxxxxxx/
v1 -> v2:
- https://lore.kernel.org/all/20220520195303.58692-1-jon@xxxxxxxxxxx/
- Addressed comments on approach from Sean.
v2 -> v3:
- Addressed comments on approach from Sean.
arch/x86/kvm/vmx/vmx.c | 62 ++++++++++++++++++++----------------------
1 file changed, 29 insertions(+), 33 deletions(-)
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 610355b9ccce..1c725d17d984 100644
--- a/arch/x86/kvm/vmx/vmx.c
+++ b/arch/x86/kvm/vmx/vmx.c
@@ -2057,20 +2057,32 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return 1;
vmx->spec_ctrl = data;
- if (!data)
+
+ /*
+ * Disable interception on the first non-zero write, unless the
+ * guest is hosted on an eIBRS system and setting only
+ * SPEC_CTRL_IBRS, which is typically set once at boot and never
+ * touched again. All other bits are often set on a per-task
+ * basis, i.e. may change frequently, so the benefit of avoiding
+ * VM-exits during guest context switches outweighs the cost of
+ * RDMSR on every VM-Exit to save the guest's value.
+ */
+ if (!data ||
+ (data == SPEC_CTRL_IBRS &&
+ (vcpu->arch.arch_capabilities & ARCH_CAP_IBRS_ALL)))
break;
/*
- * For non-nested:
- * When it's written (to non-zero) for the first time, pass
- * it through.
- *
- * For nested:
- * The handling of the MSR bitmap for L2 guests is done in
- * nested_vmx_prepare_msr_bitmap. We should not touch the
- * vmcs02.msr_bitmap here since it gets completely overwritten
- * in the merging. We update the vmcs01 here for L1 as well
- * since it will end up touching the MSR anyway now.
+ * Update vmcs01.msr_bitmap even if L2 is active, i.e. disable
+ * interception for the vCPU on the first write regardless of
+ * whether the WRMSR came from L1 or L2. vmcs02's bitmap is a
+ * combination of vmcs01 and vmcs12 bitmaps, and will be
+ * recomputed by nested_vmx_prepare_msr_bitmap() on the next
+ * nested VM-Enter. Note, this does mean that future WRMSRs
+ * from L2 will be intercepted until the next nested VM-Exit if
+ * L2 was the first to write, but L1 exposing the MSR to L2
+ * without first writing it is unlikely and not worth the
+ * extra bit of complexity.
*/
vmx_disable_intercept_for_msr(vcpu,
MSR_IA32_SPEC_CTRL,
@@ -2098,15 +2110,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
/*
- * For non-nested:
- * When it's written (to non-zero) for the first time, pass
- * it through.
- *
- * For nested:
- * The handling of the MSR bitmap for L2 guests is done in
- * nested_vmx_prepare_msr_bitmap. We should not touch the
- * vmcs02.msr_bitmap here since it gets completely overwritten
- * in the merging.
+ * Disable interception on the first IBPB, odds are good IBPB
+ * will be a frequent guest action. See the comment for
+ * MSR_IA32_SPEC_CTRL for details on the nested interaction.
*/
vmx_disable_intercept_for_msr(vcpu, MSR_IA32_PRED_CMD, MSR_TYPE_W);
break;
@@ -6887,19 +6893,9 @@ static fastpath_t vmx_vcpu_run(struct kvm_vcpu *vcpu)
vmx_vcpu_enter_exit(vcpu, vmx);
/*
- * We do not use IBRS in the kernel. If this vCPU has used the
- * SPEC_CTRL MSR it may have left it on; save the value and
- * turn it off. This is much more efficient than blindly adding
- * it to the atomic save/restore list. Especially as the former
- * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
- *
- * For non-nested case:
- * If the L01 MSR bitmap does not intercept the MSR, then we need to
- * save it.
- *
- * For nested case:
- * If the L02 MSR bitmap does not intercept the MSR, then we need to
- * save it.
+ * Save SPEC_CTRL if it may have been written by the guest, the current
+ * value in hardware is used by x86_spec_ctrl_restore_host() to avoid
+ * WRMSR if the current value matches the host's desired value.
*/
if (unlikely(!msr_write_intercepted(vmx, MSR_IA32_SPEC_CTRL)))
vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
--
2.30.1 (Apple Git-130)
