On Tue, Mar 8, 2022 at 2:29 AM Like Xu <like.xu.linux@xxxxxxxxx> wrote:
>
> On 8/3/2022 9:24 am, Jim Mattson wrote:
> > The third nybble of AMD's event select overlaps with Intel's IN_TX and
> > IN_TXCP bits. Therefore, we can't use AMD64_RAW_EVENT_MASK on Intel
> > platforms that support TSX.
>
> We already have pmu->reserved_bits as the first wall to check "can't use".
That is only a safeguard for Intel platforms that *don't* support TSX.
> >
> > Declare a raw_event_mask in the kvm_pmu structure, initialize it in
> > the vendor-specific pmu_refresh() functions, and use that mask for
> > PERF_TYPE_RAW configurations in reprogram_gp_counter().
> >
> > Fixes: 710c47651431 ("KVM: x86/pmu: Use AMD64_RAW_EVENT_MASK for PERF_TYPE_RAW")
>
> Is it really a fix ?
When I submitted the commit referenced above, it was not my intention
to introduce semantic changes on Intel platforms. I hadn't realized at
the time that IN_TX and IN_TXCP overlapped with bits 11:8 of AMD's
event select.
But, you are right. Previously, the code would mask off IN_TX and
IN_TXCP, just to or them back in again later. So, the aforementioned
commit did not change the semantics of the existing code; it just
rendered the statements to or the bits back in redundant.
