On 3/8/22 11:28, Like Xu wrote:
On 8/3/2022 9:24 am, Jim Mattson wrote:
The third nybble of AMD's event select overlaps with Intel's IN_TX and
IN_TXCP bits. Therefore, we can't use AMD64_RAW_EVENT_MASK on Intel
platforms that support TSX.
We already have pmu->reserved_bits as the first wall to check "can't use".
Declare a raw_event_mask in the kvm_pmu structure, initialize it in
the vendor-specific pmu_refresh() functions, and use that mask for
PERF_TYPE_RAW configurations in reprogram_gp_counter().
Fixes: 710c47651431 ("KVM: x86/pmu: Use AMD64_RAW_EVENT_MASK for
PERF_TYPE_RAW")
Is it really a fix ?
No, it's not, so I'm queuing it for 5.18 only.
Paolo
