Re: [PATCH] Enable non page boundary BAR device assignment

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On 10.12.2009, at 11:56, Michael S. Tsirkin wrote:

> On Thu, Dec 10, 2009 at 12:37:37PM +0200, Muli Ben-Yehuda wrote:
>> On Thu, Dec 10, 2009 at 11:31:01AM +0100, Alexander Graf wrote:
>> 
>>>> What do you have in mind for such a rewrite?
>>> 
>>> I'd like to see it more well-abstracted and versatile. I don't see
>>> an obvious reason why we shouldn't be able to use a physical device
>>> in a TCG target :-).
>> 
>> mmio and pio are easy, DMA you'd need an IOMMU for security, or
>> whatever uio does just for translation,
> 
> uio currently does not support DMA, but I plan to fix this
> 
>> and interrupts you probably
>> get for free from uio. Seems eminently doable to me. Why you'd want to
>> is another matter :-)
>> 
>> Cheers,
>> Muli
> 
> The list above ignores the biggest issue: you would have to change TCG
> code generation to make this work.
> 
> For example, I think a read memory barrier is currently ignored in
> translation, and host CPU will reorder reads.  Some drivers might also
> rely on ordering guarantees that depend on CPU cacheline sizes.  Atomics
> is another bag of tricks but I expect atomics on a DMA memory are not
> widely used.

Since we'd use the mmio callbacks for MMIO we'd be strictly ordered, no?

Alex
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