On Thu, Nov 18, 2021, Paolo Bonzini wrote: > The IRTE for an assigned device can trigger a POSTED_INTR_VECTOR even > if APICv is disabled on the vCPU that receives it. In that case, the > interrupt will just cause a vmexit and leave the ON bit set together > with the PIR bit corresponding to the interrupt. > > Right now, the interrupt would not be delivered until APICv is re-enabled. > However, fixing this is just a matter of always doing the PIR->IRR > synchronization, even if the vCPU has temporarily disabled APICv. > > This is not a problem for performance, or if anything it is an > improvement. First, in the common case where vcpu->arch.apicv_active is > true, one fewer check has to be performed. Second, static_call_cond will > elide the function call if APICv is not present or disabled. Finally, > in the case for AMD hardware we can remove the sync_pir_to_irr callback: > it is only needed for apic_has_interrupt_for_ppr, and that function > already has a fallback for !APICv. > > Cc: stable@xxxxxxxxxxxxxxx > Co-developed-by: Sean Christopherson <seanjc@xxxxxxxxxx> For my bits: Signed-off-by: Sean Christopherson <seanjc@xxxxxxxxxx>
