This patch adds id_reg_info for ID_AA64MMFR0_EL1 to make it
writable by userspace.
Since ID_AA64MMFR0_EL1 stage 2 granule size fields don't follow the
standard ID scheme, we need a special handling to validate those fields.
Signed-off-by: Reiji Watanabe <reijiw@xxxxxxxxxx>
---
arch/arm64/kvm/sys_regs.c | 118 ++++++++++++++++++++++++++++++++++++++
1 file changed, 118 insertions(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 83b05d37afbd..7c1ac456dc94 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -508,6 +508,113 @@ static int validate_id_aa64isar1_el1(struct kvm_vcpu *vcpu,
return 0;
}
+/*
+ * Check if the requested stage2 translation granule size indicated in
+ * @mmfr0 is also indicated in @mmfr0_lim. This function assumes that
+ * the stage1 granule size indicated in @mmfr0 has been validated already.
+ */
+static int aa64mmfr0_tgran2_check(int field, u64 mmfr0, u64 mmfr0_lim)
+{
+ s64 tgran2, lim_tgran2, rtgran1;
+ int f1;
+ bool is_signed = true;
+
+ tgran2 = cpuid_feature_extract_unsigned_field(mmfr0, field);
+ lim_tgran2 = cpuid_feature_extract_unsigned_field(mmfr0_lim, field);
+ if (tgran2 == lim_tgran2)
+ return 0;
+
+ if (tgran2 && lim_tgran2)
+ return (tgran2 > lim_tgran2) ? -E2BIG : 0;
+
+ /*
+ * Either tgran2 or lim_tgran2 is zero.
+ * Need stage1 granule size to validate tgran2.
+ */
+ switch (field) {
+ case ID_AA64MMFR0_TGRAN4_2_SHIFT:
+ f1 = ID_AA64MMFR0_TGRAN4_SHIFT;
+ break;
+ case ID_AA64MMFR0_TGRAN64_2_SHIFT:
+ f1 = ID_AA64MMFR0_TGRAN64_SHIFT;
+ break;
+ case ID_AA64MMFR0_TGRAN16_2_SHIFT:
+ f1 = ID_AA64MMFR0_TGRAN16_SHIFT;
+ is_signed = false;
+ break;
+ default:
+ /* Should never happen */
+ WARN_ONCE(1, "Unexpected stage2 granule field (%d)\n", field);
+ return 0;
+ }
+
+ /*
+ * If tgran2 == 0 (&& lim_tgran2 != 0), the requested stage2 granule
+ * size is indicated in the stage1 granule size field of @mmfr0.
+ * So, validate the stage1 granule size against the stage2 limit
+ * granule size.
+ * If lim_tgran2 == 0 (&& tgran2 != 0), the stage2 limit granule size
+ * is indicated in the stage1 granule size field of @mmfr0_lim.
+ * So, validate the requested stage2 granule size against the stage1
+ * limit granule size.
+ */
+
+ /* Get the relevant stage1 granule size to validate tgran2 */
+ if (tgran2 == 0)
+ /* The requested stage1 granule size */
+ rtgran1 = cpuid_feature_extract_field(mmfr0, f1, is_signed);
+ else /* lim_tgran2 == 0 */
+ /* The stage1 limit granule size */
+ rtgran1 = cpuid_feature_extract_field(mmfr0_lim, f1, is_signed);
+
+ /*
+ * Adjust the value of rtgran1 to compare with stage2 granule size,
+ * which indicates: 1: Not supported, 2: Supported, etc.
+ */
+ if (is_signed)
+ /* For signed, -1: Not supported, 0: Supported, etc. */
+ rtgran1 += 0x2;
+ else
+ /* For unsigned, 0: Not supported, 1: Supported, etc. */
+ rtgran1 += 0x1;
+
+ if ((tgran2 == 0) && (rtgran1 > lim_tgran2))
+ /*
+ * The requested stage1 granule size (== the requested stage2
+ * granule size) is larger than the stage2 limit granule size.
+ */
+ return -E2BIG;
+ else if ((lim_tgran2 == 0) && (tgran2 > rtgran1))
+ /*
+ * The requested stage2 granule size is larger than the stage1
+ * limit granulze size (== the stage2 limit granule size).
+ */
+ return -E2BIG;
+
+ return 0;
+}
+
+static int validate_id_aa64mmfr0_el1(struct kvm_vcpu *vcpu,
+ const struct id_reg_info *id_reg, u64 val)
+{
+ u64 limit = id_reg->vcpu_limit_val;
+ int ret;
+
+ ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN4_2_SHIFT, val, limit);
+ if (ret)
+ return ret;
+
+ ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN64_2_SHIFT, val, limit);
+ if (ret)
+ return ret;
+
+ ret = aa64mmfr0_tgran2_check(ID_AA64MMFR0_TGRAN16_2_SHIFT, val, limit);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
{
u64 limit = id_reg->vcpu_limit_val;
@@ -601,6 +708,16 @@ static struct id_reg_info id_aa64isar1_el1_info = {
.get_reset_val = get_reset_id_aa64isar1_el1,
};
+static struct id_reg_info id_aa64mmfr0_el1_info = {
+ .sys_reg = SYS_ID_AA64MMFR0_EL1,
+ .ftr_check_types = S_FCT(ID_AA64MMFR0_TGRAN4_SHIFT, FCT_LOWER_SAFE) |
+ S_FCT(ID_AA64MMFR0_TGRAN64_SHIFT, FCT_LOWER_SAFE) |
+ U_FCT(ID_AA64MMFR0_TGRAN4_2_SHIFT, FCT_IGNORE) |
+ U_FCT(ID_AA64MMFR0_TGRAN64_2_SHIFT, FCT_IGNORE) |
+ U_FCT(ID_AA64MMFR0_TGRAN16_2_SHIFT, FCT_IGNORE),
+ .validate = validate_id_aa64mmfr0_el1,
+};
+
/*
* An ID register that needs special handling to control the value for the
* guest must have its own id_reg_info in id_reg_info_table.
@@ -614,6 +731,7 @@ static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {
[IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info,
[IDREG_IDX(SYS_ID_AA64ISAR0_EL1)] = &id_aa64isar0_el1_info,
[IDREG_IDX(SYS_ID_AA64ISAR1_EL1)] = &id_aa64isar1_el1_info,
+ [IDREG_IDX(SYS_ID_AA64MMFR0_EL1)] = &id_aa64mmfr0_el1_info,
};
static int validate_id_reg(struct kvm_vcpu *vcpu,
--
2.33.1.1089.g2158813163f-goog
