On 2021/9/30 16:49, Tian, Kevin wrote:
From: Jason Gunthorpe <jgg@xxxxxxxxxx>
Sent: Thursday, September 23, 2021 8:22 PM
These are different things and need different bits. Since the ARM path
has a lot more code supporting it, I'd suggest Intel should change
their code to use IOMMU_BLOCK_NO_SNOOP and abandon
IOMMU_CACHE.
I didn't fully get this point. The end result is same, i.e. making the DMA
cache-coherent when IOMMU_CACHE is set. Or if you help define the
behavior of IOMMU_CACHE, what will you define now?
It is clearly specifying how the kernel API works:
!IOMMU_CACHE
must call arch cache flushers
IOMMU_CACHE -
do not call arch cache flushers
IOMMU_CACHE|IOMMU_BLOCK_NO_SNOOP -
dot not arch cache flushers, and ignore the no snoop bit.
Who will set IOMMU_BLOCK_NO_SNOOP? I feel this is arch specific
knowledge about how cache coherency is implemented, i.e.
when IOMMU_CACHE is set intel-iommu driver just maps it to
blocking no-snoop. It's not necessarily to be an attribute in
the same level as IOMMU_CACHE?
On Intel it should refuse to create a !IOMMU_CACHE since the HW can't
do that.
Agree. In reality I guess this is not hit because all devices are marked
coherent on Intel platforms...
Baolu, any insight here?
I am trying to follow the discussion here. Please guide me if I didn't
get the right context.
Here, we are discussing arch_sync_dma_for_cpu() and
arch_sync_dma_for_device(). The x86 arch has clflush to sync dma buffer
for device, but I can't see any instruction to sync dma buffer for cpu
if the device is not cache coherent. Is that the reason why x86 can't
have an implementation for arch_sync_dma_for_cpu(), hence all devices
are marked coherent?
Thanks
Kevin
Best regards,
baolu
