On Wed, Sep 22, 2021 at 03:24:07PM -0600, Alex Williamson wrote:
> On Sun, 19 Sep 2021 14:38:38 +0800
> Liu Yi L <yi.l.liu@xxxxxxxxx> wrote:
>
> > +struct iommu_device_info {
> > + __u32 argsz;
> > + __u32 flags;
> > +#define IOMMU_DEVICE_INFO_ENFORCE_SNOOP (1 << 0) /* IOMMU enforced snoop */
>
> Is this too PCI specific, or perhaps too much of the mechanism rather
> than the result? ie. should we just indicate if the IOMMU guarantees
> coherent DMA? Thanks,
I think the name of "coherent DMA" for this feature inside the kernel
is very, very confusing. We already have something called coherent dma
and this usage on Intel has nothing at all to do with that.
In fact it looks like this confusing name has already caused
implementation problems as I see dma-iommu, is connecting
dev->dma_coherent to IOMMU_CACHE! eg in dma_info_to_prot(). This is
completely wrong if IOMMU_CACHE is linked to no_snoop.
And ARM seems to have fallen out of step with x86 as the ARM IOMMU
drivers are mapping IOMMU_CACHE to ARM_LPAE_PTE_MEMATTR_OIWB,
ARM_LPAE_MAIR_ATTR_IDX_CACHE
The SMMU spec for ARMv8 is pretty clear:
13.6.1.1 No_snoop
Support for No_snoop is system-dependent and, if implemented, No_snoop
transforms a final access attribute of a Normal cacheable type to
Normal-iNC-oNC-OSH downstream of (or appearing to be performed
downstream of) the SMMU. No_snoop does not transform a final access
attribute of any-Device.
Meaning setting ARM_LPAE_MAIR_ATTR_IDX_CACHE from IOMMU_CACHE does NOT
block non-snoop, in fact it *enables* it - the reverse of what Intel
is doing!
So this is all a mess.
Better to start clear and unambiguous names in the uAPI and someone
can try to clean up the kernel eventually.
The required behavior for iommufd is to have the IOMMU ignore the
no-snoop bit so that Intel HW can disable wbinvd. This bit should be
clearly documented for its exact purpose and if other arches also have
instructions that need to be disabled if snoop TLPs are allowed then
they can re-use this bit. It appears ARM does not have this issue and
does not need the bit.
What ARM is doing with IOMMU_CACHE is unclear to me, and I'm unclear
if/how iommufd should expose it as a controllable PTE flag. The ARM
Jason
