On 16/09/21 20:45, Wei Huang wrote:
According to AMD APM, Volume 2: System Programming (Rev. 3.37, March 2021), CR4 register is defined to have the following MBZ reserved bits: * Bit 12 - 15 * Bit 19 * Bit 24 - 63 Additionally Bit 12 will be used by LA57 in future CPUs. Fix the CR4 reserved bit definition to match with APM and prevent potential test_cr4() failures.
So the difference is LA57 and CET. Queued, thanks! Paolo
-#define SVM_CR4_LEGACY_RESERVED_MASK 0xff88f000U +#define SVM_CR4_LEGACY_RESERVED_MASK 0xff08e000U
