According to AMD APM, Volume 2: System Programming (Rev. 3.37, March 2021),
CR4 register is defined to have the following MBZ reserved bits:
* Bit 12 - 15
* Bit 19
* Bit 24 - 63
Additionally Bit 12 will be used by LA57 in future CPUs. Fix the CR4
reserved bit definition to match with APM and prevent potential test_cr4()
failures.
Reported-by: Babu Moger <Babu.Moger@xxxxxxx>
Signed-off-by: Wei Huang <wei.huang2@xxxxxxx>
Tested-by: Babu Moger <Babu.Moger@xxxxxxx>
---
x86/svm.h | 4 ++--
x86/svm_tests.c | 6 +-----
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/x86/svm.h b/x86/svm.h
index ae35d0844788..f74b13adb068 100644
--- a/x86/svm.h
+++ b/x86/svm.h
@@ -352,8 +352,8 @@ struct __attribute__ ((__packed__)) vmcb {
#define SVM_CR3_LONG_MBZ_MASK 0xfff0000000000000U
#define SVM_CR3_LONG_RESERVED_MASK 0x0000000000000fe7U
#define SVM_CR3_PAE_LEGACY_RESERVED_MASK 0x0000000000000007U
-#define SVM_CR4_LEGACY_RESERVED_MASK 0xff88f000U
-#define SVM_CR4_RESERVED_MASK 0xffffffffff88f000U
+#define SVM_CR4_LEGACY_RESERVED_MASK 0xff08e000U
+#define SVM_CR4_RESERVED_MASK 0xffffffffff08e000U
#define SVM_DR6_RESERVED_MASK 0xffffffffffff1ff0U
#define SVM_DR7_RESERVED_MASK 0xffffffff0000cc00U
#define SVM_EFER_RESERVED_MASK 0xffffffffffff0200U
diff --git a/x86/svm_tests.c b/x86/svm_tests.c
index b998b247d87c..547994df065a 100644
--- a/x86/svm_tests.c
+++ b/x86/svm_tests.c
@@ -2383,13 +2383,9 @@ skip_npt_only:
vmcb->save.cr4 = cr4_saved;
}
+/* Test CR4 MBZ bits based on legacy or long modes */
static void test_cr4(void)
{
- /*
- * CR4 MBZ bits based on different modes:
- * [15:12], 17, 19, [31:22] - legacy mode
- * [15:12], 17, 19, [63:22] - long mode
- */
u64 cr4_saved = vmcb->save.cr4;
u64 efer_saved = vmcb->save.efer;
u64 efer = efer_saved;
--
2.31.1
