On Sun, Aug 08, 2021 at 11:33:44PM -0500, Wei Huang wrote: > > > On 8/8/21 11:27 PM, Yu Zhang wrote: > > On Sun, Aug 08, 2021 at 11:11:40PM -0500, Wei Huang wrote: > > > > > > > > > On 8/8/21 10:58 PM, Yu Zhang wrote: > > > > On Sun, Aug 08, 2021 at 02:26:56PM -0500, Wei Huang wrote: > > > > > AMD future CPUs will require a 5-level NPT if host CR4.LA57 is set. > > > > > > > > Sorry, but why? NPT is not indexed by HVA. > > > > > > NPT is not indexed by HVA - it is always indexed by GPA. What I meant is NPT > > > page table level has to be the same as the host OS page table: if 5-level > > > page table is enabled in host OS (CR4.LA57=1), guest NPT has to 5-level too. > > > > I know what you meant. But may I ask why? > > I don't have a good answer for it. From what I know, VMCB doesn't have a > field to indicate guest page table level. As a result, hardware relies on > host CR4 to infer NPT level. I guess you mean not even in the N_CR3 field of VMCB? Then it's not a broken design - it's a limitation of SVM. :) B.R. Yu
