On 2021-05-12 13:59, Zenghui Yu wrote:
Hi Eric,
On 2021/5/6 20:30, Auger Eric wrote:
running the test on 5.12 I get
==== Test Assertion Failure ====
aarch64/debug-exceptions.c:232: false
pid=6477 tid=6477 errno=4 - Interrupted system call
1 0x000000000040147b: main at debug-exceptions.c:230
2 0x000003ff8aa60de3: ?? ??:0
3 0x0000000000401517: _start at :?
Failed guest assert: hw_bp_addr == PC(hw_bp) at
aarch64/debug-exceptions.c:105
values: 0, 0x401794
FYI I can also reproduce it on my VHE box. And Drew's suggestion [*]
seemed to work for me. Is the ISB a requirement of architecture?
Very much so. Given that there is no context synchronisation (such as
ERET or an interrupt) in this code, the CPU is perfectly allowed to
delay the system register effect as long as it can.
M.
--
Jazz is not dead. It just smells funny...
