Re: [PATCH v4 01/16] perf/x86/intel: Add x86_pmu.pebs_vmx for Ice Lake Servers

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 





On 2021/4/6 20:47, Andi Kleen wrote:
AFAIK, Icelake supports adaptive PEBS and extended PEBS which Skylake
doesn't.
But we can still use IA32_PEBS_ENABLE MSR to indicate general-purpose
counter in Skylake.
Is there anything else that only Icelake supports in this patches set?
Only Icelake server has the support for recovering from a EPT violation
on the PEBS data structures. To use it on Skylake server you would
need to pin the whole guest, but that is currently not done.
Sorry. Some questions about "Pin the whole guest". Do you mean VmPin equals VmSize in "/proc/$(pidof qemu-kvm)/status"? Or just VmLck equals VmSize? Or something else?
Besides, we have tried this patches set in Icelake.  We can use pebs(eg:
"perf record -e cycles:pp")
when guest is kernel-5.11, but can't when kernel-4.18.  Is there a minimum
guest kernel version requirement?
You would need a guest kernel that supports Icelake server PEBS. 4.18
would need backports for tht.


-Andi




[Index of Archives]     [KVM ARM]     [KVM ia64]     [KVM ppc]     [Virtualization Tools]     [Spice Development]     [Libvirt]     [Libvirt Users]     [Linux USB Devel]     [Linux Audio Users]     [Yosemite Questions]     [Linux Kernel]     [Linux SCSI]     [XFree86]

  Powered by Linux