On Thu, Apr 23, 2020 at 09:56:31AM -0700, Sean Christopherson wrote: > On Thu, Mar 26, 2020 at 04:18:46PM +0800, Yang Weijiang wrote: > > Set the feature bits so that CET capabilities can be seen > > in guest via CPUID enumeration. Add CR4.CET bit support > > in order to allow guest set CET master control bit(CR4.CET). > > > > Signed-off-by: Yang Weijiang <weijiang.yang@xxxxxxxxx> > > --- > > arch/x86/include/asm/kvm_host.h | 3 ++- > > arch/x86/kvm/cpuid.c | 4 ++++ > > 2 files changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h > > index 2c944ad99692..5109c43c6981 100644 > > --- a/arch/x86/include/asm/kvm_host.h > > +++ b/arch/x86/include/asm/kvm_host.h > > @@ -95,7 +95,8 @@ > > | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR | X86_CR4_PCIDE \ > > | X86_CR4_OSXSAVE | X86_CR4_SMEP | X86_CR4_FSGSBASE \ > > | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_VMXE \ > > - | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP)) > > + | X86_CR4_SMAP | X86_CR4_PKE | X86_CR4_UMIP \ > > + | X86_CR4_CET)) > > > > #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR) > > > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > > index 25e9a11291b3..26ab959df92f 100644 > > --- a/arch/x86/kvm/cpuid.c > > +++ b/arch/x86/kvm/cpuid.c > > @@ -366,6 +366,10 @@ void kvm_set_cpu_caps(void) > > kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); > > if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) > > kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); > > + if (boot_cpu_has(X86_FEATURE_IBT)) > > + kvm_cpu_cap_set(X86_FEATURE_IBT); > > + if (boot_cpu_has(X86_FEATURE_SHSTK)) > > + kvm_cpu_cap_set(X86_FEATURE_SHSTK); > > This is the wrong way to advertise bits, the correct method is to declare > the flag in the appriorate kvm_cpu_cap_mask() call. The manually handling > is only needed when the feature bit diverges from kernel support, either > because KVM allow a feature based purely on hardware support, e.g. LA57, or > when emulating a feature based on a different similar feature, e.g. the > STIBP/SSBD flags above. > > diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c > index 6828be99b908..6262438f9527 100644 > --- a/arch/x86/kvm/cpuid.c > +++ b/arch/x86/kvm/cpuid.c > @@ -329,7 +329,8 @@ void kvm_set_cpu_caps(void) > F(AVX512VBMI) | F(LA57) | 0 /*PKU*/ | 0 /*OSPKE*/ | F(RDPID) | > F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | > F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | > - F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ > + F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | > + F(SHSTK) > ); > /* Set LA57 based on hardware capability. */ > if (cpuid_ecx(7) & F(LA57)) > @@ -338,7 +339,7 @@ void kvm_set_cpu_caps(void) > kvm_cpu_cap_mask(CPUID_7_EDX, > F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | > F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | > - F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) > + F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | F(IBT) > ); > Aah, thanks a lot for the explanation, will fix them. > > > > kvm_cpu_cap_mask(CPUID_7_1_EAX, > > F(AVX512_BF16) > > -- > > 2.17.2 > >
