On Thu, 2 Apr 2020 at 07:01, Sean Christopherson
<sean.j.christopherson@xxxxxxxxx> wrote:
>
> On Wed, Apr 01, 2020 at 05:40:03PM +0000, Nadav Amit wrote:
> > > On Mar 31, 2020, at 11:46 PM, Wanpeng Li <kernellwp@xxxxxxxxx> wrote:
> > >
> > > Cc more people,
> > > On Wed, 1 Apr 2020 at 08:35, Paolo Bonzini <pbonzini@xxxxxxxxxx> wrote:
> > >> On 01/04/20 02:19, Wanpeng Li wrote:
> > >>> - /* No delay here, so we always clear the pending bit */
> > >>> - val &= ~(1 << 12);
> > >>> + /* Immediately clear Delivery Status in xAPIC mode */
> > >>> + if (!apic_x2apic_mode(apic))
> > >>> + val &= ~(1 << 12);
> > >>
> > >> This adds a conditional, and the old behavior was valid according to the
> > >> SDM: "software should not assume the value returned by reading the ICR
> > >> is the last written value".
> > >
> > > Nadav, Sean, what do you think?
> >
> > I do not know. But if you write a KVM unit-test, I can run it on bare-metal
> > and give you feedback about how it behaves.
>
> I agree with Paolo, clearing the bit doesn't violate the SDM. The
> conditional is just as costly as the AND, if not more so, even for x2APIC.
>
> I would play it safe and clear the bit even in the x2APIC only path to
> avoid tripping up guest kernels that loop on the delivery status even when
> using x2APIC.
Fair enough.
Wanpeng
